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8th International Workshop on
Software and Compilers for Embedded Systems
SCOPES 2004
Workshop Program - Presentation Abstract
| Suppression of redundant operations in reverse compiled code using global dataflow analysis |
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| Adrian Johnstone - Royal Holloway, University of London Elizabeth Scott - Royal Holloway, University of London |
| We describe an unusual application of dataflow analysis to reverse compilation from assembler source to ANSI-C. Most real architectures support (or more usually, mandate) the use of register-based operands in computations and provide status bits which are set as an implicit side-effect of arithmetic instructions. Naive translation of these semantics into C yields programs which are dominated by references to registers and the calculation of status results. The target processor for our reverse compiler is particularly prone to these effects since the functional units are surrounded by pipeline registers which must be loaded and unloaded around each computation, but the problem is common to all reverse compilers: how to render the computational core of a low-level algorithm in high level code that is comfortable for a human to read and which maintains the low level semantics. We apply a brute-force dataflow analysis to provide exact use-define information at all program points and then follow the use-define relationships to back-substitute expressions in an effort to remove register references. We also suppress dead status code calculations and perform limited alias analysis for some special purpose registers which can be accessed via more than one name. We show that use of these techniques can significantly reduce the degree to which the underlying architecture 'shows through' into the resulting C translation and that the computation times required are manageable for one-off translations. |
Presentation
