Home

About Scopes

Call for Papers

Committee

Important Dates

Workshop Program

Registration

Publication

Hotel Information

Travel Information

Contact

SCOPES'03

LCTES-SCOPES'02

SCOPES'01

8th International Workshop on

Software and Compilers for Embedded Systems

SCOPES 2004

Workshop Program - Presentation Abstract

Automatically Customising VLIW Architectures with Coarse Grained Application-specific Functional Units
Diviya Jain - Department of Computer Science and Engineering, Indian Institute of Technology Delhi, India
Laura Pozzi - Processor Architecture Laboratory, Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland
Paolo Ienne - Processor Architecture Laboratory, Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland
Anshul Kumar - Department of Computer Science and Engineering, Indian Institute of Technology Delhi, India
Instruction Level Parallelism (ILP) machines, such as Very Long Instruction Word (VLIW) architectures, and customised architectures are two paradigms that have been used in the past in order to increase the performance of processors. While a VLIW machine has multiple functional units and can issue more than one operation per cycle, a customised processor is equipped with Application-specific Functional Units (AFUs), designed specifically for an application. The benefit of customised architectures has been proven on simple, single issue machines, but a question lays still unanswered on what effect customisation can have on multiple issue machines. Is a VLIW machine already powerful enough to nullify the benefit given by customisation? Or are the two benefits orthogonal and can therefore be exploited together? In this paper, we answer positively to the latter question. We experimentally prove that insertion of automatically identified AFUs can increase performance of a VLIW architecture, even when its issue-width and register file size has been pushed to the maximum. We prove that the presence of AFUs can allow the ILP processor designer to trade off either issue-width, or, more importantly, the register file size. To prove our points, we have customised the Trimaran architecture and toolchain framework, in order to model in a very precise way the presence of AFUs. Moreover, AFUs are automatically identified within the new framework. Incidentally, we show the complexity of adding instruction-set extension support to a legacy toolchain, and discuss many of the involved challenges.

Presentation